cha2092b rohs compliant ref. : dscha20921233 21-august-01 1/6 specifications subject to change without notice united monolithic semiconductors s.a.s. route dpartementale 128 - b.p.46 - 91401 orsay cede x france tel. : +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 33 03 09 18-32ghz low noise amplifier gaas monolithic microwave ic description the cha2092 is a high gain broadband three- stage monolithic low noise amplifier. it is designed for a wide range of applications, from military to commercial communication systems. the backside of the chip is both rf and dc ground. this helps simplify the assembly process. self biasing technique is implemented on chip to ease the circuit biasing. the circuit is manufactured with a phemt process, 0.25m gate length, via holes through the substrate, air bridges and electron beam gate lithography. it is available in chip form. main features broadband performances: 18-32ghz 2.5db noise figure 10dbm output power (-1db gain comp.) 22db 1.0db gain low dc power consumption, 60ma @ 3.5v chip size: 1.67 x 0.97 x 0.10mm vgs1 vgs2,3 vds in out 8831 0 5 10 15 20 25 30 15 17 19 21 23 25 27 29 31 33 35 frequency (ghz) gain & nf ( db ) main characteristics tamb. = 25c symbol parameter min typ max unit fop operating frequency range 18 32 ghz g small signal gain 17 22 db nf noise figure (20-32ghz) 2.5 3.5 db p1db output power at 1db gain compression 8 10 dbm id bias current 60 100 ma esd protection : electrostatic discharge sensitive device. observe handling precautions !
cha2092b 18-32ghz low noise amplifier ref. : dscha20921233 21-august-01 2/6 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 electrical characteristics tamb = +25c, vds = 3.5v; ids=60ma symbol parameter min typ max min typ max unit fop operating frequency range (1) 20 28 18 32 ghz g small signal gain (1) 18 22 17 22 db d g small signal gain flatness (1) 1.5 2.5 db d gsb gain flatness over 40mhz 0.5 0.5 dbpp is reverse isolation (1) 25 30 25 30 db p1db output power at 1db gain compression (3) 8 10 8 10 dbm vswrin input vswr (1) 2.5:1 3.0:1 2.5:1 3.5:1 vswrout output vswr (1) 2.5:1 3.0:1 2.5:1 3.5:1 nf 18-20ghz noise figure (2) 20-28ghz 28-32ghz 2.5 3.5 2.5 2.5 2.5 4 3.5 3.5 db vd dc voltage vd vgs1,vgs2&3 3.5 -0.5 4.5 3.5 -0.5 4.5 v v id bias current (2) 60 100 60 100 ma (1)these values are representative of on-wafer meas urements that are made without bonding wires at the rf ports. (2) 60 ma is the typical bias current used for on w afer measurements, with vgs1 and vgs2&3 connected together. for optimum noise figure, the b ias current could be reduced down to 50 ma, adjusting the vgs1 voltage. (3) ids=90ma absolute maximum ratings tamb. = 25c (1) symbol parameter values unit vd drain bias voltage 5.0 v id drain bias current 120 ma vg gate bias voltage -2.0 to +0.4 v pin maximum peak input power overdrive (2) +15 dbm ta operating temperature range -40 to +85 c tstg storage temperature range -55 to +155 c (1) operation of this device above anyone of these parameters may cause permanent damage. (2) duration < 1s.
18-32ghz low noise amplifier cha2092b ref. : dscha20921233 21-august-01 3/6 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical results tamb=25c 15,00 16,00 17,00 18,00 19,00 20,00 21,00 22,00 23,00 24,00 25,00 17,00 19,00 21,00 23,00 25,00 27,00 29,00 31,00 33,00 35,00 frequency (ghz) gain (db) 0,00 1,00 2,00 3,00 4,00 5,00 6,00 7,00 8,00 9,00 10,00 nf (db) dbs21 nf gain and nf vs frequency (vdd=3.5v; ids=60ma) 0 5 10 15 20 25 20 21 22 23 24 25 26 27 28 29 30 frequency (ghz) gain (db) vgs1=-0.36v vgs1=-0.5v vgs1=-0.6v vgs1=-0,7v vgs1=-0,8v vgs1=-0,9v vgs1=-1v gain vs frequency and vgs1 (vdd=3.5v; vgs23=-0.3v) 0 5 10 15 20 25 20 21 22 23 24 25 26 27 28 29 30 frequency (ghz) gain (db) vgs=-0,7v vgs=-0.6v vgs=-0.5v vgs=-0.4v vgs=-0.3v gain vs frequency and vgs123 (vdd=3.5v)
cha2092b 18-32ghz low noise amplifier ref. : dscha20921233 21-august-01 4/6 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 -16 -14 -12 -10 -8 -6 -4 -2 0 20,00 21,00 22,00 23,00 24,00 25,00 26,00 27,00 28,00 29,00 3 0,00 frequency (ghz) dbs11 (db) -0,36 -0,50 -0,60 -0,70 -0,80 -0,90 -1,00 dbs11 vs frequency and vgs1 (vdd=3.5v; vgs23=-0.3v) - 20,0 40,0 60,0 80,0 100,0 120,0 -0,70 -0,65 -0,60 -0,55 -0,50 -0,45 -0,40 -0,35 -0,30 vgs123 (v) ids (ma) ids vs vgs123 (vdd=3.5v)
18-32ghz low noise amplifier cha2092b ref. : dscha20921233 21-august-01 5/6 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 chip assembly and mechanical data in out 100pf 100pf to vdd dc drain supply feed to vgs dc gate supply feed. 100pf to vgs dc gate supply feed to ajust nf. 8831 note : supply feed should be capacitively bypassed. 1670 +/ - 10 1005 385 325 970 +/ - 10 385 920 8831 bonding pad positions. (chip thickness: 100m. all dimensions are in micro meters)
cha2092b 18-32ghz low noise amplifier ref. : dscha20921233 21-august-01 6/6 specifications subject to change without notice route dpartementale 128 , b.p.46 - 91401 orsay ce dex - france tel.: +33 (0)1 69 33 03 08 - fax : +33 (0)1 69 3 3 03 09 typical bias tuning the circuit schematic is given below: in out vd 1,2,3 vg 2,3 vg 1 the three drain biases are connected altogether on chip. for typical operation, all the gate biases are connected together at the same power sup ply, tuned to drive a small signal operating current of 60 ma. a separate access to th e gate voltages of the first stage ( vg1 ) and the second and third stages ( vgs2,3 ) is provi ded for the fine tuning of the amplifier regarding the application. ordering information chip form : cha2092b99f/00 information furnished is believed to be accurate an d reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by impli cation or otherwise under any patent or patent rights of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and re places all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or s ystems without express written approval from united monolithic semiconductors s.a.s.
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